1. Field of the Invention
This invention relates to the field of data processing devices. More particularly, the invention relates to data processing devices having a memory for storing data.
2. Description of the Prior Art
It is known to provide data processing systems with a memory for storing code and data. In such systems, memory power consumption can be an important issue. For example, dynamic random access memory (DRAM) can contribute up to 35% of total energy consumption in some systems. Memory power consumption is a particularly important issue for server systems, where cooling costs should be kept low, and for battery powered devices, where it is desirable to prolong the battery lifetime.
Non-volatile memory technologies are now available which consume much less idle power than DRAM. For example, for flash memory devices static power consumption is of the order of tens of microwatts per gigabyte of stored data, as opposed to hundreds of milliwatts per gigabyte for DRAM. However, for non-volatile memory devices the access latency is several orders of magnitude greater than for DRAM. This means that replacing DRAM with flash memory, for example, would severely affect system performance, wasting energy as tasks would be completed more slowly. This is particularly important for write accesses, as for example, DRAM can be written to in 55 ns, compared with 35 μs for multi-level cell phase-change random access memory (PCRAM), 200 μs for single-level cell NAND flash, and 800 μs for multi-level cell NAND flash. This means that at present non-volatile memory cannot be used as a direct replacement for DRAM memory.
Ye et al have proposed a hybrid memory system in “Prototyping a Hybrid Main Memory Using a Virtual Machine Monitor”, Proceedings of the 26th International Conference on Computer Design, ICCD 2008, 12-15 Oct. 2008, Lake Tahoe, Calif., USA, pages 272 to 279. They propose a system having a first-level memory of conventional DRAM and a second-level memory comprising non-volatile memory such as flash memory. However, they report that in order to prevent system performance being degraded by more than 10%, at least 75% of the total memory capacity must be made up of DRAM. This does not provide significant energy savings.
The present invention seeks to address this problem and provide a memory system which has a low power consumption but which also provides rapid access to stored data.
Zheng et al have proposed a DRAM system partitioned into “mini ranks” (see Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM Symposium on, 8-12 Nov. 2008, pages 210-221).